Complement Accumulator – CPL A
CPLA logically complements each bit of the Accumulator (one’s complement). Bits which previously contained a 1 are changed to a 0 and vice-versa. No flags are affected.A slash ( / ) preceding the operand in the assembly language indicates that the logical complement of the bit.
Encoding: 1 1 1 1 0 1 0 0
The Accumulator contains 5CH (01011100B). The following instruction,
CPL A
leaves the Accumulator set to 0A3H (10100011B).
Complement bit – CPL bit
CPL bit complements the bit variable specified. A bit that had been a 1 is changed to 0 and vice-versa. No other flags are affected. CLR can operate on the carry or any directly addressable bit. A slash ( / ) preceding the operand in the assembly language indicates that the logical complement of the bit.
Note: When this instruction is used to modify an output pin, the value used as the original data is read from the output data latch, not the input pin.
Encoding: 1 0 1 1 0 0 1 0 bit address
Port 1 has previously been written with 5BH (01011101B). The following instruction sequence,
CPL P1.1
CPL P1.2
leaves the port set to 5BH (01011011B).
Complement Carry Flag – CPL C
CPL C logically complement Carry Flag
Encoding: 1 0 1 1 0 0 1 1
The carry flag contains 1B. The following instruction,
CPL C
leaves the carry flag set to 0B.
CPLA logically complements each bit of the Accumulator (one’s complement). Bits which previously contained a 1 are changed to a 0 and vice-versa. No flags are affected.A slash ( / ) preceding the operand in the assembly language indicates that the logical complement of the bit.
Encoding: 1 1 1 1 0 1 0 0
The Accumulator contains 5CH (01011100B). The following instruction,
CPL A
leaves the Accumulator set to 0A3H (10100011B).
Complement bit – CPL bit
CPL bit complements the bit variable specified. A bit that had been a 1 is changed to 0 and vice-versa. No other flags are affected. CLR can operate on the carry or any directly addressable bit. A slash ( / ) preceding the operand in the assembly language indicates that the logical complement of the bit.
Note: When this instruction is used to modify an output pin, the value used as the original data is read from the output data latch, not the input pin.
Encoding: 1 0 1 1 0 0 1 0 bit address
Port 1 has previously been written with 5BH (01011101B). The following instruction sequence,
CPL P1.1
CPL P1.2
leaves the port set to 5BH (01011011B).
Complement Carry Flag – CPL C
CPL C logically complement Carry Flag
Encoding: 1 0 1 1 0 0 1 1
The carry flag contains 1B. The following instruction,
CPL C
leaves the carry flag set to 0B.
Related topics:
8051 Set Bit | 8051 Clear Accumulator and Bit | 8051 Rotate Accumulator | 8051 Swap Nibble | 8051 Exchange Accumulator | 8051 Exchange Digit | 8051 Push and Pop | 8051 No Operation
List of topics: 8051
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