Increment
Instruction | INC byte |
---|---|
Function | Increment |
Description | INC increments the indicated variable by 1. An original value of 0FFH overflows to 00H. No flags are affected. Three addressing modes are allowed: register, direct, or register-indirect. Note: When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. |
Example | Register 0 contai ns 7EH (011111110B) . I nternal RAM l ocati ons 7EH and 7FH contain 0FFH and 40H, respectively. The following instruction sequence, INC @R0 INC R0 INC @R0 leaves register 0 set to 7FH and internal RAM locations 7EH and 7FH holding 00H and 41H, respectively. |
Variants | INC A INC Rn INC direct address INC @Ri |
Instruction | INC A |
---|---|
Bytes | 1 |
Cycles | 1 |
Encoding | 0 0 0 0 0 1 0 0 |
Operation | A = A + 1 |
Flags Affected | C AC F0 RS1 RS0 OV P |
Example | INC A |
Bytes: Number of bytes required to encode the instruction. Cycles: Number of instruction cycles required to execute the instruction. Note that there are 12 oscillator cycles to one instruction cycle on a standard 8051. Encoding: Lists the byte encoding for the instruction. Operation: Lists, step-by-step, the operations performed by the instruction. Flags Affected: are highlighted in Bold |
Instruction | INC Rn |
---|---|
Bytes | 1 |
Cycles | 1 |
Encoding | 0 0 0 0 1 n n n |
Operation | Rn = Rn + 1 |
Flags Affected | C AC F0 RS1 RS0 OV P |
Example | INC R4 |
Bytes: Number of bytes required to encode the instruction. Cycles: Number of instruction cycles required to execute the instruction. Note that there are 12 oscillator cycles to one instruction cycle on a standard 8051. Encoding: Lists the byte encoding for the instruction. Operation: Lists, step-by-step, the operations performed by the instruction. Flags Affected: are highlighted in Bold |
Instruction | INC direct address |
---|---|
Bytes | 2 |
Cycles | 1 |
Encoding | 0 0 0 0 0 1 0 1 A7...A0 |
Operation | (direct) = (direct) + 1 |
Flags Affected | C AC F0 RS1 RS0 OV P |
Example | INC 34h |
Bytes: Number of bytes required to encode the instruction. Cycles: Number of instruction cycles required to execute the instruction. Note that there are 12 oscillator cycles to one instruction cycle on a standard 8051. Encoding: Lists the byte encoding for the instruction. Operation: Lists, step-by-step, the operations performed by the instruction. Flags Affected: are highlighted in Bold |
Instruction | INC @Ri |
---|---|
Bytes | 1 |
Cycles | 1 |
Encoding | 0 0 0 0 0 1 1 i |
Operation | (Ri) = (Ri) + 1 |
Flags Affected | C AC F0 RS1 RS0 OV P |
Example | INC @R0 |
Bytes: Number of bytes required to encode the instruction. Cycles: Number of instruction cycles required to execute the instruction. Note that there are 12 oscillator cycles to one instruction cycle on a standard 8051. Encoding: Lists the byte encoding for the instruction. Operation: Lists, step-by-step, the operations performed by the instruction. Flags Affected: are highlighted in Bold |
Instruction | INC DPTR |
---|---|
Function | Increment Data Pointer |
Bytes | 1 |
Cycles | 2 |
Encoding | 1 0 1 0 0 0 1 1 |
Operation | DPTR = DPTR + 1 |
Description | INC DPTR increments the 16-bit data pointer by 1. A 16-bit increment (modulo 216) is performed, and an overflow of the low-order byte of the data pointer (DPL) from 0FFH to 00H increments the high-order byte (DPH). No flags are affected. This is the only 16-bit register which can be incremented. |
Flags Affected | C AC F0 RS1 RS0 OV P |
Example | Registers DPH and DPL contain 12H and 0FEH, respectively. The following instruction sequence, INC DPTR INC DPTR INC DPTR changes DPH and DPL to 13H and 01H. |
Bytes: Number of bytes required to encode the instruction. Cycles: Number of instruction cycles required to execute the instruction. Note that there are 12 oscillator cycles to one instruction cycle on a standard 8051. Encoding: Lists the byte encoding for the instruction. Operation: Lists, step-by-step, the operations performed by the instruction. Flags Affected: are highlighted in Bold |
Related topics:
8051 Arithmetic Operation Instructions | 8051 ADD Instruction | 8051 ADDC Instruction | 8051 SUBB Instruction | 8051 DEC Instruction | 8051 MUL Instruction | 8051 DIV Instruction | 8051 DA Instruction
List of topics: 8051
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