Logical AND
| Instruction | ANL dest-byte,src-byte |
|---|---|
| Function | Logical-AND for byte variables |
| Description | ANL performs the bitwise logical-AND operation between the variables indicated and stores the results in the destination variable. No flags are affected. The two operands allow six addressing mode combinations. When the destination is the Accumulator, the source can use register, direct, register-indirect, or immediate addressing; when the destination is a direct address, the source can be the Accumulator or immediate data. Note: When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. |
| Example | If the Accumulator holds 0C3H (1100001lB), and register 0 holds 55H (01010101B), then the following instruction, ANL A,R0 leaves 41H (01000001B) in the Accumulator. When the destination is a directly addressed byte, this instruction clears combinations of bits in any RAM location or hardware register. The mask byte determining the pattern of bits to be cleared would either be a constant contained in the instruction or a value computed in the Accumulator at run-time. The following instruction, ANL P1,#01110011B clears bits 7, 3, and 2 of output port 1. |
| Variants | ANL A,Rn ANL A,direct address ANL A,@Ri ANL A,#immediate data ANL direct address,A ANL direct address, #immediate data |
| Instruction | ANL A,Rn |
|---|---|
| Bytes | 1 |
| Cycles | 1 |
| Encoding | 0 1 0 1 1 n n n |
| Operation | A = A AND Rn |
| Flags Affected | C AC F0 RS1 RS0 OV P |
| Example | ANL A, R4 |
| Bytes: Number of bytes required to encode the instruction. Cycles: Number of instruction cycles required to execute the instruction. Note that there are 12 oscillator cycles to one instruction cycle on a standard 8051. Encoding: Lists the byte encoding for the instruction. Operation: Lists, step-by-step, the operations performed by the instruction. Flags Affected: are highlighted in Bold | |
| Instruction | ANL A,direct address |
|---|---|
| Bytes | 2 |
| Cycles | 1 |
| Encoding | 0 1 0 1 0 1 0 1 A7...A0 |
| Operation | A = A AND (direct address) |
| Flags Affected | C AC F0 RS1 RS0 OV P |
| Example | ANL A, 40h |
| Bytes: Number of bytes required to encode the instruction. Cycles: Number of instruction cycles required to execute the instruction. Note that there are 12 oscillator cycles to one instruction cycle on a standard 8051. Encoding: Lists the byte encoding for the instruction. Operation: Lists, step-by-step, the operations performed by the instruction. Flags Affected: are highlighted in Bold | |
| Instruction | ANL A,@Ri |
|---|---|
| Bytes | 1 |
| Cycles | 1 |
| Encoding | 0 1 0 1 0 1 1 i |
| Operation | A = A AND (Ri) |
| Flags Affected | C AC F0 RS1 RS0 OV P |
| Example | ANL A, @R0 |
| Bytes: Number of bytes required to encode the instruction. Cycles: Number of instruction cycles required to execute the instruction. Note that there are 12 oscillator cycles to one instruction cycle on a standard 8051. Encoding: Lists the byte encoding for the instruction. Operation: Lists, step-by-step, the operations performed by the instruction. Flags Affected: are highlighted in Bold | |
| Instruction | ANL A,#immediate data |
|---|---|
| Bytes | 2 |
| Cycles | 1 |
| Encoding | 0 1 0 1 0 1 0 0 D7...D0 |
| Operation | A = A AND immediate data |
| Flags Affected | C AC F0 RS1 RS0 OV P |
| Example | ANL A, #3Fh |
| Bytes: Number of bytes required to encode the instruction. Cycles: Number of instruction cycles required to execute the instruction. Note that there are 12 oscillator cycles to one instruction cycle on a standard 8051. Encoding: Lists the byte encoding for the instruction. Operation: Lists, step-by-step, the operations performed by the instruction. Flags Affected: are highlighted in Bold | |
| Instruction | ANL direct address,A |
|---|---|
| Bytes | 2 |
| Cycles | 1 |
| Encoding | 0 1 0 1 0 0 1 0 A7...A0 |
| Operation | (direct address) = (direct address) AND A |
| Flags Affected | C AC F0 RS1 RS0 OV P |
| Example | ANL 40h, A |
| Bytes: Number of bytes required to encode the instruction. Cycles: Number of instruction cycles required to execute the instruction. Note that there are 12 oscillator cycles to one instruction cycle on a standard 8051. Encoding: Lists the byte encoding for the instruction. Operation: Lists, step-by-step, the operations performed by the instruction. Flags Affected: are highlighted in Bold | |
| Instruction | ANL direct address, #immediate data |
|---|---|
| Bytes | 3 |
| Cycles | 2 |
| Encoding | 0 1 0 1 0 0 1 1 A7...A0 D7...D0 |
| Operation | (direct address) = (direct address) AND immediate data |
| Flags Affected | C AC F0 RS1 RS0 OV P |
| Example | ANL 30h, #77h |
| Bytes: Number of bytes required to encode the instruction. Cycles: Number of instruction cycles required to execute the instruction. Note that there are 12 oscillator cycles to one instruction cycle on a standard 8051. Encoding: Lists the byte encoding for the instruction. Operation: Lists, step-by-step, the operations performed by the instruction. Flags Affected: are highlighted in Bold | |
| Instruction | ANL C,src-bit |
|---|---|
| Function | Logical-AND for bit variables |
| Description | If the Boolean value of the source bit is a logical 0, then ANL C clears the carry flag; otherwise, this instruction leaves the carry flag in its current state. A slash ( / ) preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value, but the source bit itself is not affected. No other flags are affected. Only direct addressing is allowed for the source operand. |
| Example | Set the carry flag if, and only if, P1.0 = 1, ACC.7 = 1, and OV = 0: MOV C,P1.0 ;LOAD CARRY WITH INPUT PIN STATE ANL C,ACC.7 ;AND CARRY WITH ACCUM. BIT 7 ANL C,/OV ;AND WITH INVERSE OF OVERFLOW FLAG |
| Variants | ANL C,bit ANL C,/bit |
| Instruction | ANL C,bit |
|---|---|
| Bytes | 2 |
| Cycles | 2 |
| Encoding | 10000010 bit_address |
| Operation | C = C AND (bit) |
| Flags Affected | C AC F0 RS1 RS0 OV P |
| Example | ANL C, 22h |
| Bytes: Number of bytes required to encode the instruction. Cycles: Number of instruction cycles required to execute the instruction. Note that there are 12 oscillator cycles to one instruction cycle on a standard 8051. Encoding: Lists the byte encoding for the instruction. Operation: Lists, step-by-step, the operations performed by the instruction. Flags Affected: are highlighted in Bold | |
| Instruction | ANL C,/bit |
|---|---|
| Bytes | 2 |
| Cycles | 2 |
| Encoding | 1 0 1 1 0 0 0 0 bit_address |
| Operation | C = C AND NOT (bit) |
| Flags Affected | C AC F0 RS1 RS0 OV P |
| Example | ANL C, /22h |
| Bytes: Number of bytes required to encode the instruction. Cycles: Number of instruction cycles required to execute the instruction. Note that there are 12 oscillator cycles to one instruction cycle on a standard 8051. Encoding: Lists the byte encoding for the instruction. Operation: Lists, step-by-step, the operations performed by the instruction. Flags Affected: are highlighted in Bold | |
Related topics:
8051 Logical Operation Instructions | 8051 ORL Instruction | 8051 XRL Instruction | 8051 CLR Instruction | 8051 CPL Instruction | 8051 RL Instruction | 8051 RR Instruction | 8051 RLC Instruction | 8051 RRC Instruction | 8051 SWAP Instruction
List of topics: 8051
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